Lead Design Engineer

Job Summary

Cadence is seeking passionate leaders and innovators eager to make a meaningful impact in the technology sector. We provide a dynamic environment where skilled professionals can thrive, collaborate, and contribute to pioneering advancements in analog integrated circuit design and layout. Join us to work on cutting-edge projects that shape the future of semiconductor technology.

Key Responsibilities

As an Analog Layout Designer at Cadence, you will be responsible for hands-on layout design of a variety of analog IP blocks. These include operational amplifiers (Opamps), bandgap references, data converters, low-dropout regulators (LDOs), phase-locked loops (PLLs), and high-speed analog circuits such as SerDes. You will analyze how layout influences critical circuit parameters like speed, capacitance, power consumption, and area efficiency.

Your role will involve applying advanced analog layout techniques, including device matching, shielding, and enforcing floorplan constraints to optimize circuit performance and reliability. You will also integrate IP blocks at the chip level, taking into account the overall floorplan and system-level requirements.

A strong understanding of deep submicron (DSM) technology methodologies, challenges, and design rules—especially for technology nodes at 28nm and below—is essential. Collaboration is key; you will work closely with cross-functional teams, communicating clearly and contributing as a proactive team player.

To enhance productivity and accuracy, you will utilize scripting and automation tools in your layout processes. Additionally, you will prepare detailed technical documentation and deliver presentations to internal teams and stakeholders. Strong analytical and problem-solving skills will be critical as you tackle complex design challenges.

Required Qualifications

Candidates should hold a Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field (BE/BTech/ME/MS/MTech). Proven hands-on experience in analog layout design across the specified IP blocks is required.

A solid grasp of how analog layout impacts circuit performance and familiarity with DSM technology considerations are necessary. Excellent written, verbal, and presentation communication skills are essential for effective collaboration and knowledge sharing.

The ability to work collaboratively across diverse teams and geographies is important. Candidates must demonstrate strong problem-solving aptitude and meticulous attention to detail.

Preferred Qualifications and Additional Skills

Experience with advanced technology nodes at 28nm or below is highly desirable. Familiarity with scripting and automation tools to streamline layout workflows will be considered a strong asset.

Behavioral competencies sought include the ability to build strong working relationships with peers and management, creatively explore innovative solutions, and maintain integrity while striving for excellence.

At Cadence, we are dedicated to work that truly matters. Join us to solve complex challenges that few can tackle and be part of a team that continuously pushes the boundaries of technology innovation.